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Sheet目录3827

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2003 Microchip Technology Inc.

DS39582B-page 65

PIC16F87XA

8.1

Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin RC2/CCP1. An event is defined as one of the

following:

Every falling edge

Every rising edge

Every 4th rising edge

Every 16th rising edge

The type of event is configured by control bits,

CCP1M3:CCP1M0 (CCPxCON<3:0>). When a cap-

ture is made, the interrupt request flag bit, CCP1IF

(PIR1<2>), is set. The interrupt flag must be cleared in

software. If another capture occurs before the value in

overwritten by the new value.

8.1.1

CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be

configured as an input by setting the TRISC<2> bit.

FIGURE 8-1:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

8.1.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode, or Synchro-

nized Counter mode, for the CCP module to use the

capture feature. In Asynchronous Counter mode, the

capture operation may not work.

8.1.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit, CCP1IF, following any such

change in operating mode.

8.1.4

CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in Capture mode,

the prescaler counter is cleared. Any Reset will clear

the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore, the first capture may be from

a non-zero prescaler. Example 8-1 shows the recom-

mended

method

for

switching

between

capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 8-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

Note:

If the RC2/CCP1 pin is configured as an

output, a write to the port can cause a

Capture condition.

CCPR1H

CCPR1L

TMR1H

TMR1L

Set Flag bit CCP1IF

(PIR1<2>)

Capture

Enable

CCP1CON<3:0>

RC2/CCP1

Prescaler

÷ 1, 4, 16

and

Edge Detect

CLRF

CCP1CON

; Turn CCP module off

MOVLW

NEW_CAPT_PS

; Load the W reg with

; the new prescaler

; move value and CCP ON

MOVWF

CCP1CON

; Load CCP1CON with this

; value

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